1. Technical Field
The present invention relates to the field of electronic devices and, in particular, to electronic devices for driving signals onto bus traces.
2. Related Art
Modern processors can operate at core frequencies in excess of 200 MHz. In order to take advantage of these high core frequencies, computer systems must be able to transmit signals among their components at roughly comparable frequencies. Preferably, the signal buses used to transmit these signals operate at frequencies that are a third or more of the processor frequency. At high frequencies, bus traces behave like transmission lines, where impedance mismatches lead to signal reflection and interference effects. These effects distort rapidly slewing signals and are compounded by the trend to operate computers at lower system voltages. The lower operating frequencies of buses relative to those of processors are due in part to these factors.
Increasing processor speeds are widening the disparity between core (processor) and bus frequencies, increasing the likelihood that a processor will be idled by bottlenecks on its associated buses. The impact of this frequency mismatch is particularly evident in multiprocessor systems, where more than one device operates at high frequency, and the activities of these devices must be coordinated through bus signals. For example, currently available systems based on the Pentium.TM. and Pentium Pro.TM. processors of Intel Corporation have core frequencies on the order of 200 MHz and employ a 66 MHz front side bus for communications among the processors, chip set logic, and cluster logic. The next generation of processors will operate at frequencies approaching 300 MHz or more. A 66 MHz bus will be inadequate for communicating data among such fast processors. Bus frequencies on the order of 100 MHz or more will be necessary to fully support the performance advantages of these processors.
The limitations of currently available bus systems are illustrated by the front side bus currently used in the Pentium Pro system. This bus is a modification of the Gunning Transceiver Logic (GTL) bus and is referred to as the GTL+ bus. The GTL+ bus is an open drain bus that includes RC elements for slew rate control and pull up resisters to a termination voltage. The terminating resistors are selected to match the impedance of the bus trace and the stubs used to connect devices, e.g. processors, to the bus. The stubs are typically not terminated and their presence makes it difficult to estimate the trace impedance. These factors make impedance matching difficult and exacerbates noise problems at higher frequencies.
In systems employing GTL-type buses, processors on the front side bus assert selected signals by driving a zero onto the corresponding trace, i.e. these signals are asserted low. An N-channel transistor driven by the processor actively pulls the line low when the processor asserts the signal. The terminating resistors pull the trace high when the processor ceases to assert the signal. At higher frequencies, the active pull-down N-channel transistor keeps high to low voltage transitions relatively clean. However, the passive pull-up action provided by the terminating resistors allows signals to undergo substantial ringing and signal distortion on low to high voltage transitions. The terminating voltage and other parameters of the system constrain any solutions that are required to retain compatibility with the current front side bus. For example, CMOS push-pull drivers provide relatively clean signals for transitions in both directions by including pull-up and pull-down transistors for driving high-going and low-going transitions, respectively. However, these transistors turn on and off according to the state of the driver and are incompatible with shared, open drain buses like GTL and GTL+.